An integrated circuit device is comprised of several layers of metal that are separated by insulating layers also called intermetal dielectric (IMD) layers. Contact or via holes are formed in the IMD layers and are filled with a conductive material to connect one metal layer with another. A popular material for an IMD layer is silicon oxide with a dielectric constant (k) equal to about 4. However, with the constant need to reduce the size of metal interconnects in order to provide devices with higher performance, a dielectric layer having a lower k value is necessary. A material with a lower dielectric constant will be more effective in preventing capacitance coupling or crosstalk between metal lines. Fluorine doped SiO2 or fluorosilicate glass (FSG) has a k value of about 3.5 or slightly less depending on the fluorine content. Therefore, newer technologies are incorporating FSG as a preferred dielectric layer.
Implementing FSG in a manufacturing scheme is not done without reliability issues. FSG films have a tendency to absorb water that can be released in later stages of fabrication and cause corrosion in adjacent metal features. Moreover, loosely held fluorine can diffuse out of the dielectric layer and form HF which then attacks metal such as copper, aluminum or tungsten to cause metal corrosion that degrades device performance. Several manufacturers have added an oxide liner between an FSG layer and a metal feature to prevent fluorine from attacking the metal.
For example, in U.S. Pat. No. 6,380,066, a double layer of oxide is employed to protect a metal plug from an FSG layer. Two oxide layers are deposited on a first layer of metal before FSG is deposited and a metal plug is formed in an oxide layer.
U.S. Pat. Nos. 6,319,814 and 6,410,106 to UMC stress the importance of process conditions in forming an FSG layer. Generally, a high density plasma (HDP) chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) technique is used to deposit an FSG film. These patents claim that an HDP CVD process with no RF bias and no ion bombardment coupled with no backside cooling on the wafer chuck enables an FSG layer to be formed that is resistant to water uptake. In addition, improved adhesion and film uniformity on a silicon nitride or silicon oxynitride etch stop layer in a damascene structure is observed.
U.S. Pat. No. 6,300,672 mentions the use of a silicon oxynitride (SiON) cap on FSG to protect an overlying metal layer. The key feature is that SiON functions both as an anti-reflective (ARC) layer and as a barrier to fluorine diffusion since it is a denser material than the oxide matrix which contains fluorine.
U.S. Pat. No. 5,937,323 states that the sequence prior to flowing fluorine in a FSG deposition is critical. A heated wafer with a surface temperature above 100° C. combined with a low gas deposition flow and low RF power form a 200 Angstrom FSG film with tightly bound fluorine on an undoped silicate glass (USG) liner. The USG liner and tightly bond fluorine prevent any fluorine attack on an underlying metal layer. This process also features top and side gas flows and top and side RF generators but a bias RF power is not applied during the FSG process.
A defect that can occur during deposition of a USG layer, especially with a high ion bombardment associated with a high RF bias, is peeling of a metal anti-reflective coating (ARC) such as TiN that is located above a metal line. Thus, an improved process is needed for a USG liner that offers better protection from corrosion to metal lines and which avoids high ion bombardment that can affect adhesion of an ARC above a metal line. The method should have a good gap filling capability and be compatible with existing tools and materials.